Digital Principles and System Design MCQs with answers Page - 7

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Q. The output frequency related to the sampling interval of a frequency counter as

  • (A) directly with the sampling interval
  • (B) inversely with the sampling interval
  • (C) more precision with longer sampling interval
  • (D) less precision with longer sampling interval

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Q. In an HDL application of a stepper motor, what is done next after an up/down counter is built?

  • (A) build the sequencer
  • (B) test it on a simulator
  • (C) test the decoder
  • (D) design an intermediate integer variable

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Q. In a digital clock application, the basic frequency must be divided down as

  • (A) 1 hz
  • (B) 60 hz
  • (C) 100 hz
  • (D) 1000 hz

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Q. What does the data signal do in the keypad application?

  • (A) the row and column encoded data
  • (B) the ring encoded data
  • (C) the freeze locator data
  • (D) the ring counter data

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Q. When a key is pressed, what does the ring counter in the HDL keypad application do?

  • (A) count to find the row
  • (B) freeze
  • (C) count to find the column
  • (D) start the d flip-flop

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Q. A step which should be followed in project management is known as

  • (A) overall definition
  • (B) system documentation
  • (C) synthesis and testing
  • (D) system integration

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Q. In the keypad application, the preset state of the ring counter define

  • (A) the nanding of the columns
  • (B) the nanding of the rows
  • (C) the proper output of the column encoder
  • (D) the proper output of the row encoder

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Q. A major block which is not a part of an HDL frequency counter

  • (A) timing and control unit
  • (B) decoder/display
  • (C) display register
  • (D) bit shifter

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Q. A stepper motor HDL application must include

  • (A) sequencers and multiplexers
  • (B) types and bits
  • (C) counters and decoders
  • (D) variables and processes

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Q. 11 HDL MODELS OF COMBINATIONAL CIRCUITS

  • (A) true
  • (B) false
  • (C) ---
  • (D) ---

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