Digital Principles and System Design MCQs with answers Page - 9

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Q. The process used for implementation of sequential logic in VHDL is called process.

  • (A) sequential process
  • (B) combinational process
  • (C) clocked process
  • (D) unclocked process

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Q. Why do we need to define clock signal in the sensitivity list of the process?

  • (A) to trigger the statement as soon as there is some event on clock
  • (B) to trigger the clock signal as soon as there is some event on input
  • (C) to trigger the clock signal as soon as there is some event on output
  • (D) to trigger the statement as soon as there is some event on input

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Q. A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as

  • (A) switching condition
  • (B) master slave condition
  • (C) race around condition
  • (D) edge triggered condition

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Q. Which of the following method is not used to remove the race around condition in a flip flop?

  • (A) using level triggered flip flop
  • (B) using master slave flip flop
  • (C) using edge triggered flip flop
  • (D) all of the above are used to remove the race around

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Q. Which of the following attribute is generally used in implementation of sequential circuits?

  • (A) ‘stable
  • (B) ‘length
  • (C) ‘last_event
  • (D) ‘event

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Q. (A + B)(A’ * B’) = ?

  • (A) 1
  • (B) 0
  • (C) ab
  • (D) ab’

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Q. According to boolean law: A + 1 = ?

  • (A) 1
  • (B) a
  • (C) 0
  • (D) a’

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Q. The involution of A is equal to

  • (A) a
  • (B) a’
  • (C) 1
  • (D) 0

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Q. Simplify Y = AB’ + (A’ + B)C.

  • (A) ab’ + c
  • (B) ab + ac
  • (C) a’b + ac’
  • (D) ab + a

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Q. The boolean function A + BC is a reduced form of

  • (A) ab + bc
  • (B) (a + b)(a + c)
  • (C) a’b + ab’c
  • (D) (a + c)b

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