Digital Principles and System Design MCQs with answers Page - 23

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A

Admin • 802.91K Points
Coach

Q. The difference between a PAL & a PLA is

  • (A) pals and plas are the same thing
  • (B) the pla has a programmable or plane and a programmable and plane, while the pal only has a programmable and plane
  • (C) the pal has a programmable or plane and a programmable and plane, while the pla only has a programmable and plane
  • (D) the pal has more possible product terms than the pla

A

Admin • 802.91K Points
Coach

Q. If a PAL has been programmed once

  • (A) its logic capacity is lost
  • (B) its outputs are only active high
  • (C) its outputs are only active low
  • (D) it cannot be reprogrammed

A

Admin • 802.91K Points
Coach

Q. The FPGA refers to

  • (A) first programmable gate array
  • (B) field programmable gate array
  • (C) first program gate array
  • (D) field program gate array

A

Admin • 802.91K Points
Coach

Q. The full form of VLSI is

  • (A) very long single integration
  • (B) very least scale integration
  • (C) very large scale integration
  • (D) very long scale integration

A

Admin • 802.91K Points
Coach

Q. In FPGA, vertical and horizontal directions are separated by

  • (A) a line
  • (B) a channel
  • (C) a strobe
  • (D) a flip-flop

A

Admin • 802.91K Points
Coach

Q. Applications of PLAs are

  • (A) registered pals
  • (B) configurable pals
  • (C) pal programming
  • (D) all of the mentioned

A

Admin • 802.91K Points
Coach

Q. PAL refers to

  • (A) programmable array loaded
  • (B) programmable logic array
  • (C) programmable array logic
  • (D) programmable and logic

A

Admin • 802.91K Points
Coach

Q. For programmable logic functions, which type of PLD should be used?

  • (A) pla
  • (B) pal
  • (C) cpld
  • (D) sld

A

Admin • 802.91K Points
Coach

Q. How many two-input AND and OR gates are required to realize Y = CD+EF+G?

  • (A) 2, 2
  • (B) 2, 3
  • (C) 3, 3
  • (D) 3, 2

A

Admin • 802.91K Points
Coach

Q. The flag bits in an ALU is defined as

  • (A) the total number of registers
  • (B) the status bit conditions
  • (C) the total number of control lines
  • (D) all of the mentioned