Digital Principles and System Design MCQs with answers Page - 16

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Q. A user doesn’t want to use the IF statement for detecting clock edge. It is possible to do the same by using any other keyword in VHDL.

  • (A) true
  • (B) false
  • (C) ---
  • (D) ---

A

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Q. Sequential circuits are represented as

  • (A) finite state machine
  • (B) infinite state machine
  • (C) finite synchronous circuit
  • (D) infinite asynchronous circuit

A

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Q. Sequential circuit includes

  • (A) delays
  • (B) feedback
  • (C) delays and feedback from input to output
  • (D) delays and feedback from output to input

A

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Q. Which constitutes the test vectors in sequential circuits?

  • (A) feedback variables
  • (B) delay factors
  • (C) test patterns
  • (D) all input combinations

A

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Q. Outputs are functions of

  • (A) present state
  • (B) previous state
  • (C) next state
  • (D) present and next state

A

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Q. Which is the delay elements for clocked system?

  • (A) and gates
  • (B) or gates
  • (C) flip-flops
  • (D) multiplexers

A

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Q. Which contributes to the necessary delay element?

  • (A) flip-flops
  • (B) circuit propagation elements
  • (C) negative feedback path
  • (D) shift registers

A

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Q. In an OR gate, if A and B are two inputs and there is struck at 1 fault in B path, then output will be

  • (A) a
  • (B) 0
  • (C) 1
  • (D) b’

A

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Q. Iterative test generation method suits for circuits with

  • (A) no feedback loops
  • (B) few feedback loops
  • (C) more feedback loops
  • (D) negative feedback loops only

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Q. Which method is very time consuming?

  • (A) d-algorithm
  • (B) iterative test generation
  • (C) pseudo exhaustive method
  • (D) test generation pattern

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