Digital Principles and System Design MCQs with answers Page - 17

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Q. In this iterative test generation method, sequential logic is

  • (A) used in the same pattern
  • (B) converted to test logic
  • (C) converted to combinational logic
  • (D) converted to asynchronous logic

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Q. For a NAND gate, struck-at 1 fault in second input line cannot be detected if

  • (A) q is 1
  • (B) q is 0
  • (C) q changes from 1 to 0
  • (D) q changes from 0 to 1

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Q. In this technique, a simple fault manifests into multiple N faults.

  • (A) true
  • (B) false
  • (C) ---
  • (D) ---

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Q. The situation wherein the data of operands are not available is called

  • (A) data hazard
  • (B) stock
  • (C) deadlock
  • (D) structural hazard

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Q. The time lost due to the branch instruction is often referred to as

  • (A) latency
  • (B) delay
  • (C) branch penalty
  • (D) none of the mentioned

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Q. method is used in centralized systems to perform out of order execution.

  • (A) scorecard
  • (B) score boarding
  • (C) optimizing
  • (D) redundancy

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Q. What are the typical values of tOE?

  • (A) 10 to 20 ns for bipolar
  • (B) 25 to 100 ns for nmos
  • (C) 12 to 50 ns for cmos
  • (D) all of the mentioned

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Q. Which of the following is not a type of memory?

  • (A) ram
  • (B) fprom
  • (C) eeprom
  • (D) rom

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Q. The chip by which both the operation of read and write is performed

  • (A) ram
  • (B) rom
  • (C) prom
  • (D) eprom

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Q. RAM is also known as

  • (A) rwm
  • (B) mbr
  • (C) mar
  • (D) rom

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