Digital Electronics and Logic Design MCQs with answers Page - 42

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Q. The output of this circuit is always .

  • (A) 1
  • (B) 0
  • (C) a
  • (D) abar

A

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Q. Excess-8 code assigns to “-8”

  • (A) 1110
  • (B) 1100
  • (C) 1000
  • (D) 0

A

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Q. The voltage gain of the Inverting Amplifier is given by the relation

  • (A) vout / vin = - rf / ri
  • (B) vout / rf = - vin / ri
  • (C) rf / vin = - ri / vout
  • (D) rf / vin = ri / vout

A

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Q. LUT is acronym for

  • (A) look up table
  • (B) local user terminal
  • (C) least upper time period
  • (D) none of given options

A

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Q. The three fundamental gates are

  • (A) and, nand, xor
  • (B) or, and, nand
  • (C) not, nor, xor
  • (D) not, or, and

A

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Q. Stack is an acronym for

  • (A) fifo memory
  • (B) lifo memory
  • (C) flash memory
  • (D) bust flash memory

A

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Q. is one of the examples of synchronous inputs.

  • (A) j-k input
  • (B) en input
  • (C) preset input (pre)
  • (D) clear input (clr)

A

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Q. occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay

  • (A) race condition
  • (B) clock skew
  • (C) ripple effect
  • (D) none of given options

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Q. THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A

  • (A) gated flip- flops
  • (B) pulse triggered flip-flops
  • (C) positive- edge triggered flip-flops
  • (D) negative -edge triggere d flip- flops

A

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Q. A positive edge-triggered flip-flop changes its state when

  • (A) low-to-high transition of clock
  • (B) high-to-low transition of clock
  • (C) enable input (en) is set
  • (D) preset input (pre) is set

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