Digital Electronics and Logic Design MCQs with answers Page - 41

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Q. In a sequential circuit the next state is determined by and

  • (A) state variable, current state
  • (B) current state, flip- flop output
  • (C) current state and external input
  • (D) input and clock signal applied

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Q. The divide-by-60 counter in digital clock is implemented by using two cascading counters:

  • (A) mod-6, mod-10
  • (B) mod-50, mod-10
  • (C) mod-10, mod-50
  • (D) mod-50, mod-6

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Q. In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.

  • (A) true
  • (B) false
  • (C) ---
  • (D) ---

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Q. The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop.

  • (A) set-up time
  • (B) hold time
  • (C) pulse interval time
  • (D) pulse stability time (pst)

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Q. 74HC163 has two enable input pins which are and

  • (A) enp, ent
  • (B) eni, enc
  • (C) enp, enc
  • (D) ent, eni

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Q. to change in one input variable

  • (A) clock skew
  • (B) condition
  • (C) hold delay
  • (D) wait

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Q. The input overrides the input

  • (A) asynchronous , synchronous
  • (B) synchronous, asynchronou s
  • (C) preset input (pre), clear input (clr)
  • (D) clear input (clr), preset input (pre)

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Q. A decade counter is .

  • (A) mod-3 counter
  • (B) mod-5 counter
  • (C) mod-8 counter
  • (D) mod-10 counter

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Q. In asynchronous transmission when the transmission line is idle,

  • (A) it is set to logic low
  • (B) it is set to logic high
  • (C) remains in previous state
  • (D) state of transmissi on line is not used to start transmissi on

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