Digital Electronics and Logic Design MCQ Questions and answers

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Q. What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic?

(A) the hct series is faster.
(B) the hct series is slower.
(C) he hct series is input and output voltage compatible with ttl.
(D) the hct series is not input and output voltage compatible with ttl.

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Q. Why are the maximum value of VOL and the minimum value of VOH used to determine the noise margin rather than the typical values for these parameters?

(A) these are worst-case conditions.
(B) these are normal conditions.
(C) these are best-case conditions.
(D) it doesn matter what values are used.

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Q. What is the standard TTL noise margin?

(A) 5.0 v
(B) 0.0 v
(C) 0.8 v
(D) 0.4 v

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Q. Which logic family is characterized by a multiemitter transistor on the input?

(A) ecl
(B) cmos
(C) ttl
(D) none of the above

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Q. he problem of the VOH(min) of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of VIH(min) is usually easily overcome by:

(A) adding a fixed voltage- divider bias resistive network at the output of the ttl device
(B) avoiding this condition and only using ttl to drive ttl
(C) adding an external pull- down resistor to ground
(D) adding an external pull-up resistor to vcc

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Q. How does the 4000 series of CMOS logic compare in terms of speed and power dissipation to the standard family of TTL logic?

(A) more power dissipation and slower speed
(B) more power dissipation and faster speed
(C) less power dissipation and faster speed
(D) less power dissipation and slower speed

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Q. What should be done with unused inputs to a TTL NAND gate?

(A) let them float
(B) tie them low
(C) tie them high
(D) none of the above

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Q. Which of the following logic families has the highest maximum clock frequency?

(A) s-ttl
(B) as-ttl
(C) hs-ttl
(D) hcmos

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Q. Why is the fan-out of CMOS gates frequency dependent?

(A) each cmos input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a cmos gate.
(B) when the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal; this defines the upper operating frequency.
(C) the higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal.
(D) the input gates of the fets are predomina ntly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the number of loads that may be attached to the output of the driving gate.

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Q. What must be done to interface TTL to CMOS?

(A) a dropping resistor must be used on the cmos 12 v supply to reduce it to 5 v for the ttl.
(B) as long as the cmos supply voltage is 5 v, they can be interfaced; however, the fan-out of the ttl is limited to five cmos gates.
(C) a 5 v zener diode must be placed across the inputs of the ttl gates in order to protect them from the higher output voltages of the cmos gates.
(D) a pull-up resistor must be used between the ttl output- cmos input node and vcc; the value of rp will depend on the number of cmos gates connected to the node.

Digital Electronics and Logic Design MCQs with answers Page - 29

Q. What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic?

Q. Why are the maximum value of VOL and the minimum value of VOH used to determine the noise margin rather than the typical values for these parameters?

Q. What is the standard TTL noise margin?

Q. Which logic family is characterized by a multiemitter transistor on the input?

Q. he problem of the VOH(min) of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of VIH(min) is usually easily overcome by:

Q. How does the 4000 series of CMOS logic compare in terms of speed and power dissipation to the standard family of TTL logic?

Q. What should be done with unused inputs to a TTL NAND gate?

Q. Which of the following logic families has the highest maximum clock frequency?

Q. Why is the fan-out of CMOS gates frequency dependent?

Q. What must be done to interface TTL to CMOS?

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