Digital Logic Circuits (DLC) MCQs with answers Page - 30

Here, you will find a collection of MCQ questions on Digital Logic Circuits (DLC). Go through these questions to enhance your preparation for upcoming examinations and interviews.

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Q. Which part of a Flash memory architecture manages all chip functions?

  • (A) program verify code
  • (B) floating-gate mosfet
  • (C) command code
  • (D) input/output pins

A

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Q. How much locations an 8-bit address code can select in memory?

  • (A) 8 locations
  • (B) 256 locations
  • (C) 65,536 locations
  • (D) 131,072 locations

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Q. What is a fusing process?

  • (A) it is a process by which data is passed to the memory
  • (B) it is a process by which data is read through the memory
  • (C) it is a process by which programs are burnout to the diode/transistors
  • (D) it is a process by which data is fetched through the memory

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Q. Fusing process is

  • (A) reversible
  • (B) irreversible
  • (C) synchronous
  • (D) asynchronous

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Q. The cell type used inside a PROM is

  • (A) link cells
  • (B) metal cells
  • (C) fuse cells
  • (D) electric cells

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Q. How many types of fuse technologies are used in PROMs?

  • (A) 2
  • (B) 3
  • (C) 4
  • (D) 5

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Q. Metal links are made up of

  • (A) polycrystalline
  • (B) magnesium sulphide
  • (C) nichrome
  • (D) silicon dioxide

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Q. Silicon links are made up of

  • (A) polycrystalline silicon
  • (B) polycrystalline magnesium
  • (C) nichrome
  • (D) silicon dioxide

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Q. During programming p-n junction is

  • (A) avalanche reverse biased
  • (B) avalanche forward biased
  • (C) zener reverse biased
  • (D) zener reverse biased

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Q. The full form of FAMOS is

  • (A) floating gate avalanche injection mos
  • (B) float gate avalanche injection mos
  • (C) floating gate avalanche induction mos
  • (D) float gate avalanche induction mos

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