Digital Electronics and Logic Design MCQs with answers Page - 56

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Q. For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH.

  • (A) toggle
  • (B) set
  • (C) reset
  • (D) not change

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Q. What is the difference between a D latch and a D flip-flop?

  • (A) the d latch has a clock input.
  • (B) the d flip- flop has an enable input.
  • (C) the d latch is used for faster operation.
  • (D) the d flip- flop has a clock input.

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Q. A frequency counter

  • (A) counts pulse width
  • (B) counts no. of clock pulses in 1 second
  • (C) counts high and low range of given clock pulse
  • (D) none of given options

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Q. If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by

  • (A) nt sec
  • (B) (n-1)t sec
  • (C) n/t sec
  • (D) (2n+1)t sec

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Q. 9: Consider an RS lip-lops with both inputs set to 0. If a momentary '1' is applied at the input S,then the output

  • (A) q will flip from 0 to 1 and then back to 0
  • (B) q will flip from 0 to 1 and then back to 0
  • (C) q will flip from 1 to 0
  • (D) q will flip from 0 to 1

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Q. A ring counter is same as

  • (A) up-down counter
  • (B) parallel- counter
  • (C) shift register
  • (D) ripple carry counter

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Q. A sequential circuit outputs a ONE when an even number (> 0) of one's are input; otherwise the output is ZERO. The minimum number of states required is

  • (A) 0
  • (B) 1
  • (C) 2
  • (D) none of these

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Q. A 2 MHz signal is applied to the input of a J-K lip-lop which is operating in the 'toggle' mode. The frequency of the signal at the output will be

  • (A) 1 mhz
  • (B) 2 mhz
  • (C) 6 mhz
  • (D) 8 mhz

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Q. To subtract a signed number (the subtrahend) from another signed number (the minuend) in the 2's complement system, the minuend is .

  • (A) complemented only if it is positive
  • (B) complemente d only if it is negative
  • (C) always complemente d
  • (D) never compleme nted

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Q. The addition of two signed numbers in the 2's complement system can cause overflow. For overflow to occur both numbers must .

  • (A) be positive
  • (B) be negative
  • (C) have the same sign
  • (D) have opposite signs

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