Digital Electronics and Logic Design MCQs with answers Page - 24

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Q. In a positive logic system, logic state 1 corresponds to

  • (A) positive voltage
  • (B) higher voltage level
  • (C) zero voltage level
  • (D) lower voltage level

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Q. The commercially available 8-input multiplexer integrated circuit in the TTL family is

  • (A) 7495
  • (B) 74153
  • (C) 74154
  • (D) 74151

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Q. The logic 0 level of a CMOS logic device is approximately

  • (A) 1.2 volts
  • (B) 0.4 volts
  • (C) 0volts
  • (D) 5volts

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Q. Which ofthe following is a universal logic gate?

  • (A) or
  • (B) xor
  • (C) and
  • (D) nand

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Q. How is the noise margin of a logic family defi ned?

  • (A) voh – vol
  • (B) greater of vdd – voh and vol – gnd
  • (C) smaller of vil – vol and voh – vih
  • (D) vih – vil.

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Q. What parameter causes the main limit on fan-out of CMOS logic in high-speed applications?

  • (A) d.c. input current
  • (B) output current
  • (C) input capacitance
  • (D) power supply voltage.

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Q. The number of standard loads that the output of the gate can drive with out impairment of its normal operation is

  • (A) fan-in
  • (B) fan-out
  • (C) noise-margin
  • (D) power- dissipiatio n

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Q. Measure of power consumed by the gate when fully driven by all its inputs is

  • (A) fan-in
  • (B) fan-out
  • (C) noise-margin
  • (D) power- dissipiatio n

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Q. Fan-out is specified in terms of

  • (A) voltage
  • (B) current
  • (C) watt
  • (D) unit load

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Q. Which of the following logic family has highest fan-out

  • (A) dtl
  • (B) cmos
  • (C) rtl
  • (D) ttl

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