Digital Electronics and Logic Design MCQs with answers Page - 16

Here, you will find a collection of MCQ questions on Digital Electronics and Logic Design. Go through these questions to enhance your preparation for upcoming examinations and interviews.

To check the correct answer, simply click the View Answer button provided for each question.

Have your own questions to contribute? Click the button below to share your MCQs with others!

+ Add Question

A

Admin • 833.24K Points
Coach

Q. The active switching element used in all TTL circuits is the

  • (A) bipolar junction transistor (bjt
  • (B) field-effect transistor (fet
  • (C) metal-oxide semiconduct or field- effect transistor (mosfet
  • (D) unijunctio n transistor (uj)

A

Admin • 833.24K Points
Coach

Q. One output structure of a TTL gate is often referred to as a

  • (A) diode
  • (B) jbt arrangement
  • (C) totem-pole arrangement
  • (D) base, emitter, collector arrangeme nt

A

Admin • 833.24K Points
Coach

Q. An open-collector output requires

  • (A) a pull-down resistor
  • (B) a pull-up resistor
  • (C) no output resistor
  • (D) an output resistor

A

Admin • 833.24K Points
Coach

Q. Which is not an output state for tristate logic?

  • (A) high
  • (B) low
  • (C) high-z
  • (D) low-z

A

Admin • 833.24K Points
Coach

Q. TTL is alive and well, particularly in

  • (A) industrial applications
  • (B) millitary applications
  • (C) educational applications
  • (D) commercia lapplicatio ns

A

Admin • 833.24K Points
Coach

Q. A TTL NAND gate with IIL(max) of –1.6 mA per input drives eight TTL inputs. How much current does the drive output sink?

  • (A) –12.8 ma
  • (B) –8 ma
  • (C) –1.6 ma
  • (D) –25.6 ma

A

Admin • 833.24K Points
Coach

Q. A standard TTL circuit with a totem-pole output can sink, in the LOW state (IOL(max)),

  • (A) 16 ma
  • (B) 20 ma
  • (C) 24 ma
  • (D) 28ma

A

Admin • 833.24K Points
Coach

Q. What should be done to unused inputs on TTL gates?

  • (A) they should be left disconnected so as not to produce a load on any of the other circuits and to minimize power loading on the voltage source.
  • (B) all unused gates should be connected together and tied to v through a 1 k resistor.
  • (C) all unused inputs should be connected to an unused output; this will ensure compatible loading on both the unused inputs and unused outputs.
  • (D) unused and and nand inputs should be tied to vcc through a 1 k resistor; unused or and nor inputs should be grounded.

A

Admin • 833.24K Points
Coach

Q. Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and ICCH = 10 mA and ICCL = 23 mA. What is the power dissipation for the chip?

  • (A) 50 mw
  • (B) 82.5 mw
  • (C) 115 mw
  • (D) 165 mw

A

Admin • 833.24K Points
Coach

Q. Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate?

  • (A) yes
  • (B) no
  • (C) ---
  • (D) ---

Add MCQ in this Category

If you want to share an MCQ question in this category, it's a great idea! It will be helpful for many other students using this website.

Share Your MCQ