Digital Electronics and Logic Design MCQs with answers Page - 18

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Q. The rise time (tr) is the time it takes for a pulse to rise from its point up to its point. The fall time (tf) is the length of time it takes to fall from the to the point.

  • (A) 10%, 90%, 90%, 10%
  • (B) 90%, 10%, 10%, 90%
  • (C) 20%, 80%, 80%, 20%
  • (D) 10%, 70.7%, 70.7%, 10%

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Q. The term buffer/driver signifies the ability to provide low output currents to drive light loads.

  • (A) true
  • (B) false
  • (C) ---
  • (D) ---

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Q. PMOS and NMOS .

  • (A) represent mosfet devices utilizing either p-channel or n- channel devices exclusively within a given gate
  • (B) are enhancement -type cmos devices used to produce a series of high-speed logic known as 74hc
  • (C) represent positive and negative mos-type devices, which can be operated from differential power supplies and are compatible with operational amplifiers
  • (D) none of the above

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Q. Why is the operating frequency for CMOS devices critical for determining power dissipation?

  • (A) at low frequencies, at low frequencies, power dissipation increases.
  • (B) at high frequencies, the gate will only be able to deliver 70.7 % of rated power.
  • (C) at high frequencies, charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation.
  • (D) at high frequencie s, the gate will only be able to deliver 70.7 % of rated power and charging and dischargin g the gate capacitanc e will draw a heavy current from the power supply and thus increase power dissipation .

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Q. Ten TTL loads per TTL driver is known as:

  • (A) noise immunity
  • (B) fan-out
  • (C) power dissipation
  • (D) propagatio n delay

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Q. The problem of different current requirements when CMOS logic circuits are driving TTL logic circuits can usually be overcome by the addition of:

  • (A) a cmos inverting bilateral switch between the stages
  • (B) a ttl tristate inverting buffer between the stages
  • (C) a cmos noninverting bilateral switch between the stages
  • (D) a cmos buffer or inverting buffer

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Q. Totem-pole outputs be connected because .

  • (A) can, in parallel, sometimes higher current is required
  • (B) cannot, together, if the outputs are in opposite states excessively high currents can damage one or both devices
  • (C) should, in series, certain applications may require higher output voltage
  • (D) can, together, together they can handle larger load currents and higher output voltages

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Q. The high input impedance of MOSFETs:

  • (A) allows faster switching
  • (B) reduces input current and power dissipation
  • (C) prevents dense packing
  • (D) creates low-noise reactions

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Q. The output current capability of a single 7400 NAND gate when HIGH is called

  • (A) source current
  • (B) sink current
  • (C) ioh
  • (D) source current of ioh

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Q. The time needed for an output to change from the result of an input change is known as:

  • (A) noise immunity
  • (B) fan-out
  • (C) propagation delay
  • (D) rise time

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