Digital Electronics and Logic Design MCQs with answers Page - 54

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Q. The alternate solution for a multiplexer and a register circuit is

  • (A) parallel in / serial out shift register
  • (B) serial in / parallel out shift register
  • (C) parallel in / parallel out shift register
  • (D) serial in / serial out shift register

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Q. A synchronous decade counter will have flip-flops

  • (A) 3
  • (B) 4
  • (C) 7
  • (D) 10

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Q. In outputs depend only on the current state.

  • (A) mealy machine
  • (B) moore machine
  • (C) state reduction table
  • (D) state assignmen t table

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Q. Given the state diagram of an up/down counter, we can find

  • (A) the next state of a given present state
  • (B) the previous state of a given present state
  • (C) both the next and previous states of a given state
  • (D) the state diagram shows only the inputs/out puts of a given states

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Q. THE HOURS COUNTER IS IMPLEMENTED USING

  • (A) only a single mod- 12 counter is required
  • (B) mod-10 and mod-6 counters
  • (C) mod-10 and mod-2 counters
  • (D) a single decade counter and a flip-flop

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Q. The design and implementation of synchronous counters start from

  • (A) truth table
  • (B) k-map
  • (C) state table
  • (D) state diagram

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Q. Q2 :=Q1 OR X OR Q3 The above ABEL expression will be

  • (A) q2:= q1 $ x $ q3
  • (B) q2:= q1 # x # q3
  • (C) q2:= q1 & x & q3
  • (D) q2:= q1 ! x ! q3

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Q. Above is the circuit diagram of

  • (A) asynchronous up-counter
  • (B) asynchronou s down- counter
  • (C) synchronous up-counter
  • (D) synchrono us down- counter

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Q. The high density FLASH memory cell is implemented using

  • (A) 1 floating-gate mos transistor
  • (B) 2 floating- gate mos transistors
  • (C) 4 floating- gate mos transistors
  • (D) 6 floating- gate mos transistors

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Q. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing .

  • (A) 1110
  • (B) 111
  • (C) 1000
  • (D) 1001

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