High Performance Computing MCQs with answers Page - 23

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Q. Which of the following is a combination of several processors on a single chip?

  • (A) multicore architecture
  • (B) risc architecture
  • (C) cisc architecture
  • (D) subword parallelism

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Q. The important feature of the VLIW is .....

  • (A) ilp
  • (B) cost effectiveness
  • (C) performance
  • (D) none of the mentioned

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Q. The parallel execution of operations in VLIW is done according to the schedule determined by .....

  • (A) sk scheduler
  • (B) interpreter
  • (C) compiler
  • (D) encoder

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Q. The VLIW processors are much simpler as they do not require of .....

  • (A) computational register
  • (B) complex logic circuits
  • (C) ssd slots
  • (D) scheduling hardware

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Q. The VLIW architecture follows ..... approach to achieve parallelism.

  • (A) misd
  • (B) sisd
  • (C) simd
  • (D) mimd

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Q. Which of the following is not a Pipeline Conflicts?

  • (A) timing variations
  • (B) branching
  • (C) load balancing
  • (D) data dependency

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Q. Which of the following statements is NOT TRUE for Internal Sorting algorithms

  • (A) usually deal with small number of elements
  • (B) no of elements must be able to fit in processs main memory
  • (C) use auxilliary memory like tape or hard disk
  • (D) ususally are of type compare-exchange

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Q. Which of the following is TRUE for Bitonic Sequence
a) Monotonically increasing
b) Monotonically Decreasing
c) With cyclic shift of indices
d) First increasing then decreasing

  • (A) a) and b)
  • (B) a) and b) and d)
  • (C) a) and b) and c)
  • (D) a) and b) and c) and d)

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Q. Which of the following is NOT a BITONIC Sequence

  • (A) {8, 6, 4, 2, 3, 5, 7, 9}
  • (B) {0, 4, 8, 9, 2, 1}
  • (C) {3, 5, 7, 9, 8, 6, 4, 2}
  • (D) {1, 2, 4, 7, 6, 0, 1}

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Q. The procedure of sorting a bitonic sequence using bitonic splits is called

  • (A) bitonic merge
  • (B) bitonic split
  • (C) bitonic divide
  • (D) bitonic series

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