Embedded Real Time Operating System MCQs with answers Page - 11

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A

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Q. Which of the following is the type of SPI controller?

  • (A) Queued SPI
  • (B) Microwire
  • (C) Microwire/plus
  • (D) Quad SPI

A

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Q. How buffers are enabled in the parallel ports?

  • (A) by the data register
  • (B) by data direction register
  • (C) by individual control register
  • (D) by data and individual control register

A

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Q. Advantages of SPI are…..

  • (A) Its faster than asynchronous serial.
  • (B) The receive hardware can be a simple shift register.
  • (C) It supports multiple slaves.
  • (D) All of Above

A

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Q. Antilock brake systems, flight management systems, pacemakers are examples of ____________

  • (A) safety critical system
  • (B) hard real time system
  • (C) soft real time system
  • (D) safety critical system and hard real time system

A

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Q. Some of the properties of real time systems include ____________

  • (A) single purpose
  • (B) inexpensively mass produced
  • (C) small size
  • (D) all of the mentioned

A

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Q. The technique in which the CPU generates physical addresses directly is known as ____________

  • (A) relocation register method
  • (B) real addressing
  • (C) virtual addressing
  • (D) none of the mentioned

A

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Q. Hard real time operating system has ______________ jitter than a soft real time operating system.

  • (A) less
  • (B) more
  • (C) equal
  • (D) none of the mentioned

A

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Q. In rate monotonic scheduling ____________

  • (A) shorter duration job has higher priority
  • (B) longer duration job has higher priority
  • (C) priority does not depend on the duration of the job
  • (D) none of the mentioned

A

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Q. In which scheduling certain amount of CPU time is allocated to each process?

  • (A) earliest deadline first scheduling
  • (B) proportional share scheduling
  • (C) equal share scheduling
  • (D) none of the mentioned

A

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Q. Time duration required for scheduling dispatcher to stop one process and start another is known as ____________

  • (A) process latency
  • (B) dispatch latency
  • (C) execution latency
  • (D) interrupt latency

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