Computer Architecture MCQs with answers Page - 2

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A

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Q. The I/O interface required to connect the I/O device to the bus consists of

  • (A) address decoder and registers
  • (B) control circuits
  • (C) address decoder, registers and control circuits
  • (D) only control circuits

A

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Q. To reduce the memory access time we generally make use of

  • (A) heaps
  • (B) higher capacity ram’s
  • (C) sdram’s
  • (D) cache’s

A

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Q. is generally used to increase the apparent size of physical memory.

  • (A) secondary memory
  • (B) virtual memory
  • (C) hard-disk
  • (D) disks

A

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Q. MFC stands for

  • (A) memory format caches
  • (B) memory function complete
  • (C) memory find command
  • (D) mass format command

A

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Q. The time delay between two successive initiations of memory operation

  • (A) memory access time
  • (B) memory search time
  • (C) memory cycle time
  • (D) instruction delay

A

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Q. The decoded instruction is stored in

  • (A) ir
  • (B) pc
  • (C) registers
  • (D) mdr

A

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Q. Which registers can interact with the secondary storage?

  • (A) mar
  • (B) pc
  • (C) ir
  • (D) r0

A

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Q. During the execution of a program which gets initialized first?

  • (A) mdr
  • (B) ir
  • (C) pc
  • (D) mar

A

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Q. Which of the register/s of the processor is/are connected to Memory Bus?

  • (A) pc
  • (B) mar
  • (C) ir
  • (D) both pc and mar

A

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Q. ISP stands for

  • (A) instruction set processor
  • (B) information standard processing
  • (C) interchange standard protocol
  • (D) interrupt service procedure

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