A

Admin • 802.91K Points
Coach

Q. The following timing diagram shows flip flop.

  • (A) t flip-flop
  • (B) d flip-flop
  • (C) sr flip-flop
  • (D) jk flip-flop
Explanation by: Admin
since there is only one input to the flip flop, therefore, it can be either d or t flip flop. but, the output becomes equal to the input signal as soon as there is a positive edge of the clock therefore, it is a delay flip flop.

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